Integrated circuits using large-scale integration techniques are presently manufactured with a high degree of reliability. However, such integrated circuits contain a very large number of components so that, even with highly reliable manufacturing techniques, there is a significant probability of one or more components being defective. For example, presently manufactured dynamic random access memory (“DRAM”) devices can contain a billion components. Even though the defect rate may be less than one defect/million components, a fairly high percentage of such memory devices contain memory cells that are defective and therefore cannot be used.
The manufacturing yield of memory devices would be considerably lower, and their cost considerably higher, if it was necessary to scrap all memory devices containing one or more defects. To avoid the need to scrap memory devices in such cases, internal repair capabilities have been developed that allow defective circuit elements to be replaced by redundant circuit elements. For example, if one or more memory cells in a row of memory cells are defective, a redundant row of memory cells may be substituted for each defective row. Similarly, if one or more memory cells in a column of memory cells are defective, a redundant column of memory cells may be substituted for each defective column. This “repair” of memory devices is normally performed during post-manufacturing testing before the memory device has been packaged. The repair is typically carried out by programming banks of fuses or anti-fuses with a row or column address corresponding to a defective row of memory cells or column of memory cells, respectively.
After a memory device has been repaired as described above, the redundant rows or columns are substituted for the defective rows or columns during use as the defective row or column is addressed. Generally, each row address is compared to a bank of fuses or anti-fuses identifying defective rows, and each column address is compared to a bank of fuses or anti-fuses identifying defective columns. In the event of a match, either of two techniques is used to substitute a redundant row or column of memory cells. The first of these is an “address suppression” technique in which the activation of a row or column of memory cells corresponding to a row or column address is suppressed, and a redundant row or column of memory cells is activated instead. The principle problem with this technique results from the need to compare each row or column address received by the memory device with the addresses of defective rows or columns, respectively. Only after the received address had been compared can either the received address (in the event the addressed row or column is not defective) or the redundant address (in the event the addressed row or column is defective) be used to select a row or column of memory cells. The time required to compare the received address to addresses corresponding to defective cells delays the processing of the received address thereby slowing the rate at which memory accesses can be performed.
In a “data suppression” technique, both the addressed row or column and a redundant row or column are addressed with each memory access. While the access is occurring, the received row or column address is compared to the addresses of defective rows or columns. In the event of a match for a read memory access, the data read from the redundant memory cells are routed to a data bus of the memory device. If there is no match, the data read from memory cells corresponding to the received address are routed to a data bus of the memory device. In the event of a match for a write memory access, the data applied to the data bus of the memory device are coupled to the redundant memory cells. If there is no match, the data applied to the data bus of the memory device are coupled to the memory cells corresponding to the received address. While these data suppression techniques can avoid the delays inherent in the above-described address suppression techniques, they are able to do so only for read memory accesses. For write memory accesses, the received data cannot be coupled to the correct memory cells until received addresses have been compared to the addresses of defective memory cells. Furthermore, data suppression techniques can result in a significant increase in circuit size and complexity and therefore increase the cost of memory devices using such techniques.
There is therefore the need for a row or column redundancy method and system that does not require received addresses to be compared with the addresses of defective memory cells each time a row or column address is received.